The present disclosure relates to a solid-state imaging device.
In related art, solid-state imaging devices fabricated by forming various elements such for example as MOS (Metal-Oxide-Semiconductor) transistors and photodiodes (light receiving sections) on a semiconductor substrate are used in various technical fields. In such a solid-state imaging device, for example, a diffused region formed by an impurity layer of an N-type carrier polarity, a source/drain region of a MOS transistor, and the like are formed on an impurity layer of a P-type carrier polarity (which impurity layer will hereinafter be referred to as a P-type well).
In the solid-state imaging device of the constitution as described above, carriers flow out from peripheral parts of the source/drain region and the diffused region to the light receiving sections via the P-type well, thereby increasing dark current and thus degrading image quality. Accordingly, various techniques have been proposed in the past to solve this problem (see Japanese Patent Laid-Open Nos. 2001-156280 and 2006-24907 (hereinafter referred to as Patent Documents 1 and 2), for example).
Patent Document 1 proposes a technique for remedying the outflow of carriers to adjacent pixels by making the impurity concentration of a P-type well forming the source/drain region of a MOS transistor higher than the impurity concentration of a P-type well forming a light receiving section. In addition, Patent Document 2 proposes a technique for reducing dark current by providing a P+ guard layer between an N+ region of a photoelectric conversion section (light receiving section) and an N+ region forming a source/drain region of a MOS transistor, the N+ regions being formed on a P-type well.